This invention relates generally to very high speed integrated circuits (VHSICs), and in particular, to a command processor having a processor chip, a memory chip, and a command chip. Further the processor provides the main computational capabilities for the command processor by performing bit-slice function table lookup, coefficient multiplication, and summation on input data samples processed in parallel in each parallel channel.
Over the past decade, there has been increasing interest in the use of ROMs as key processing elements in digital signal processors and other numerical machines. For example, the TI 'S274 and 'LS275 multiplier chips are nothing more than 256.times.8 ROMs programmed to perform table lookup multiplication.
It is easy to visualize how a small 256.times.8 ROM could be programmed as a multiplier for two 4-bit inputs to produce an 8-bit result. However, except for BCD machines, a 4-bit data format is much too small to be of practical use for digital signal processing. However, as more bits are added to the input data, the size of a simple ROM multiplier of this type more than quadruples for each bit added. For example, a 1024.times.10 ROM would be required to multiply two 5-bit numbers and produce a 10 bit result. Even if the size of the output word is restricted to equal that of either input by rounding, the exponential increase in ROM size with each bit added to the input argument still obtains. Furthermore, if the use of the ROM is restricted to that of a coefficient multiplier, wherein a single input variable is multiplied by one of several selectable coefficients, there is still the exponential growth problem. For example, a 32K.times.10 ROM would be required to multiply a 10-bit input by one of 32 selectable coefficients and produce a 10-bit, rounded result.
Clearly, if ROMs used as multipliers or any other form of numeric processing elements are to be practicable, even in the age of VHSIC, some means for limiting the word size input to each ROM, without unduly restricting the word size which can be handled by the processing system as a whole, must be employed. One approach is to use the bit-slice processing method of Peled and Liu where the size of the ROM address word is determined by the number of input words instead of the number of bits per word. While this approach has merit for some processing operations, it is not a general solution.
At first glance, the Residue Number System (RNS) based on the Chinese Remainder Theorem would seem to be a solution. Using this approach, a 16-bit input, for example, could be encoded into RNS, using ROMs, into, for example, 5 5-bit bytes and each byte could be processed independently until it is desired to decode the results into the original binary number system for display or control. Unfortunately, RNS works on integers, not fractions, and you cannot easily scale large integral results back into rounded fractions without decoding out of the RNS system, scaling in binary, and recording into RNS for further operations. There are other problems associated with RNS which make it impractical for general purpose signal processing.
These drawbacks have motivated the search for alternative techniques such as memory processing circuits and lookup tables to achieve reduced chip area per function, improved processor throughput, and reduced VHSIC design cost through the use of highly regular, memory-type chip architectures.